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1 programmable v com calibrator with eeprom and output buffer isl24211 the isl24211 is an 8-bit programmable current sink that can be used in conjunction with an extern al voltage divider to generate a voltage source (v com ) positioned between the analog supply voltage and ground. the current sink?s full-scale range is controlled by an external resistor, r set . with the appropriate choice of external resistors r 1 and r 2 , the v com voltage range can be controlled between any arbitrary voltage range. the isl24211 has an 8-bit data register and 8-bit eeprom for storing both a volatile and a permanent value for its output, with an i 2 c interface to read and write to the register and eeprom. after the part is programmed, the i 2 c interface is no longer needed; on power-up the eeprom contents ar e automatically transferred to the data register, and the pre-programmed output voltage appears on the vcom_out pin. the isl24211 also features an integrated, wide-bandwidth, high output drive buffer amplifier that can directly drive the v com input of an lcd panel. the isl24211 is available in an 10 ld 3mm x 3mm tdfn package. this package has a maximum height of 0.8mm for very low profile designs. the ambient operating temperature range is -40c to +85c . features ? 8-bit, 256-step, adjustable sink current output ? 60mhz v com buffer/amplifier ? 4.5v to 19.0v analog supply range for normal operation (10.8v minimum analog supply voltage for programming) ? 2.25v to 3.6v logic supply voltage operating range ? 400khz, i 2 c interface ? on-chip 8-bit eeprom ? guaranteed monotonic over-temperature ? compatible with applicatio ns using the 7-bit isl45041 ? pb-free (rohs-compliant) ? ultra-thin 10 ld tdfn (3 x 3 x 0.8mm max) applications ?lcd panel v com generator ? electrophoretic display v com generator related literature ?an1627 ?ISL24211IRTZ-evalz evaluation board user guide? typical application micro- controller isl24211 scl sda wp dvr_out set 3.3v v dd av dd 9 6 5 4 8 7 2 3 r set r 1 r 2 lcd panel v com i 2 c port i/o pin vcom_out 10 in n 1 figure 1. typical isl24211 application february 23, 2011 fn7585.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl24211 2 fn7585.0 february 23, 2011 block diagram pin configuration isl24211 (10 ld tdfn) top view figure 2. block diagram of the isl24211 gnd i 2 c interface dac registers 8-bit eeprom scl sda wp v dd av dd set 10 9 3 6 8 7 4 5 cs dvr_out 2 1 q1 a1 vcom_out in n analog dcp and current sink v com buffer amplifer a2 (*thermal pad connects to gnd) in n dvr_out av dd 1 2 3 4 10 9 8 7 vcom_out set scl sda exposed thermal pad* 6 v dd gnd 5 wp pin descriptions pin name pin number function in n 1 negative (inverting) input of the v com buffer op amp. this pin is used to provide feedback from the end point of the v com trace. dvr_out 2 adjustable sink current output pin. the current sunk into the dvr_out pin is equal to the dac setting times the maximum adjustable sink current divided by 256. see the ?set? pin function description below (pin 9) for the maximum adjustable sink current setting. also tied to the non-inverting input of buffer amp. av dd 3 analog power supply input. bypass to gnd with 0.1f capacitor. wp 4 eeprom write protect. active low. 0 = programming disabled; 1 = programming allowed. gnd 5 ground connection. v dd 6 digital power supply input. bypass to gnd with 0.1f capacitor. sda 7 i 2 c serial data input scl 8 i 2 c clock input set 9 maximum sink current adjustment point. connect a resistor from set to gnd to set the maximum adjustable sink current of the dvr_out pin. the maximum adjustable sink current is equal to (av dd /20) divided by r set . vcom_out 10 output of the buffer amplifier pad - thermal pad should be connected to system ground plane to optimize thermal performance.
isl24211 3 fn7585.0 february 23, 2011 ordering information part number (notes 1, 2, 3) part marking interface temp range (c) package (pb-free) pkg. dwg. # ISL24211IRTZ 211z i 2 c -40 to +85 10 ld 3x3 tdfn l10.3x3a ISL24211IRTZ-evalz evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page isl24211 . for more information on msl please see techbrief tb363 .
isl24211 4 fn7585.0 february 23, 2011 absolute maximum rating s thermal information supply voltage av dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4v input voltage with respect to ground set, in n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4v scl, sda and wp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..v dd + 0.3v output voltage with respect to ground dvr_out, vcom_out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . av dd continuous output current dvr_out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma vcom_out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ma esd ratings human body model (tested per jesd22-a114) . . . . . . . . . . . . . . . . . 7kv machine model (tested per jesd22-a115). . . . . . . . . . . . . . . . . . . . 300v charged device model (tested per jesd22-c101). . . . . . . . . . . . . . . 2kv latch up (tested per jesd 78, class ii, level a). . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 10 ld tdfn package (notes 4, 5) . . . . . . . 53 11 moisture sensitivity (see technical brief tb363 ) all packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . level 1 maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions operating range av dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 19v v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25v to 3.6v ambient operating temperature . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications test conditions: v dd = 3.3v, av dd = 18v, r set = 5k , r 1 = 10k , r 2 = 10k , (see figure 5), v com_out pin connected to in n , unless otherwise specified. typicals are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c . symbol parameter test conditions min (note 6) typ max (note 6) units dc characteristics v dd v dd supply range - operating 2.25 3.6 v av dd av dd supply range supporting eeprom programming 10.8 19 v av dd av dd supply range for wide-supply operation (not supporting eeprom programming) 4.5 19 v i dd v dd supply current wp = scl = sda = v dd 95 300 a i avdd av dd supply current wp = scl = sda = v dd 3.8 6.5 ma dvr_out characteristics zse set set zero-scale error 3 lsb fse set set full-scale error 8 lsb tcv set set voltage drift 7v/c v dvr_out dvr_out voltage range i dvr_out < 0.5ma v set + 0.4 av dd v i dvr_out maximum dvr_out sink current 4 ma inl integral non-linearity 2 lsb dnl differential non-linearity 1 lsb output amplifier characteristics v os input offset voltage 2 15 mv tcv os input offset voltage drift -6.3 v/c i b input bias current 0.001 1 a cmrr common-mode rejection ratio 55 75 db psrr power supply rejection ratio 60 82 db a vol open loop gain 55 75 db v ol output swing low i l = -5ma 50 150 mv
isl24211 5 fn7585.0 february 23, 2011 v oh output swing high i l = 5ma 17.85 17.9 v i sc short circuit current (sinking) 300 430 ma short circuit current (sourcing) 450 555 ma sr slew rate (rising) 1k || 8pf load 70 116 v/s slew rate (falling) 1k || 8pf load 50 93 v/s t s settling time to 0.2% 150 ns bw -3db bandwidth 60 mhz i 2 c inputs and output v ih_i2c sda, scl logic 1 input voltage 1.44 v v il_i2c sda, scl logic 0 input voltage 0.55 v v hys_i2c sda, scl hysteresis 260 mv i l_i2c sda, scl input leakage current 1 a v ol_i2c sda output logic low i = -3ma 0.4 v v ih_wp wp input logic high 0.7v dd v v il_wp wp input logic low 0.3v dd v v hys_wp wp input hysteresis 260 mv i l_wp wp input leakage current -0.20 -0.5 -1 a i 2 c timing f clk i 2 c clock frequency 400 khz t sch i 2 c clock high time 0.6 s t scl i 2 c clock low time 1.3 s t dsp i 2 c spike rejection filter pulse width 050 ns t sds i 2 c data set up time 250 ns t sdh i 2 c data hold time 250 ns t buf i 2 c time between stop and start 200 s t sts i 2 c repeated start condition set-up 0.6 s t sth i 2 c repeated start condition hold 0.6 s t sps i 2 c stop condition set-up 0.6 s c sda sda pin capacitance 10 pf c scl scl pin capacitance 10 pf t wr eeprom write cycle time 100 ms note: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications test conditions: v dd = 3.3v, av dd = 18v, r set = 5k , r 1 = 10k , r 2 = 10k , (see figure 5), v com_out pin connected to in n , unless otherwise specified. typicals are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c . (continued) symbol parameter test conditions min (note 6) typ max (note 6) units
isl24211 6 fn7585.0 february 23, 2011 application information lcd panels have a v com (common voltage) that must be precisely set to minimize flicker. figure 3 shows a typical v com adjustment circuit using a mechanical potentiometer, and the equivalent circuit replacement using the isl24211. having a digital i 2 c interface enables automatic, digital flicker minimization during production test and alignment. after programming, the i 2 c interface has no further use theref ore, the isl24211 automatically powers up with the correct v com voltage programmed previously. the isl24211 uses a digitally co ntrollable potentiometer (dcp), with 256 steps of resolution (see figure 4) to change the current drawn at the dvr_out pin, which then changes the voltage created by the r 1 to r 2 resistor divider (see figure 5). the dvr_out voltage is then buffered by a2 to generate a buffered output voltage at the v com_out pin, capable of directly driving the v com input of an lcd panel. the amount of current sunk is controlled by the setting of the dcp, which is recalled at power-up from the isl24211?s internal eeprom. the eeprom is typically programmed during panel manufacture. as noted in the electrical specifications on page 4, the isl24211 requires a minimum av dd voltage of 10.8v for eeprom programming, but will work in normal operation (with no eeprom programming) down to 4.5v. dcp (digitally controllable potentiometer) the dcp controls the voltage that ultimately controls the set current. figure 4 shows the rela tionship between the register value and the dcp?s tap position. note that a register value of 0 selects the first step of the resist or string. the output voltage of the dcp is given in equation 1: output current sink figure 5 shows the schematic of the dvr_out current sink. the combination of amplifier a1, tr ansistor q1, and resistor r set forms a voltage-controlled current source, with the voltage determined by the dcp setting. the external r set resistor sets the full-sca le (maximum) sink current that can be pulled from the dvr_out node. the relationship between i dvr_out and register value is shown in equation 2. figure 3. mechanical adjustment replacement dvr_out set isl24211 r 1 r 2 av dd av dd v com i out v dd r set r a r c av dd v com r b r 1 = r a r 2 = r b +r c r set = r a r b + r a r c 20r b in n vcom_out v dcp registervalue 1 + 256 -------------------------------------------------- - ?? ?? av dd 20 -------------- ?? ?? = (eq. 1) figure 4. simplified schematic of dcp av dd 19r r 0 1 2 255 254 253 252 251 register value av dd 20 v dcp figure 5. current sink circuit av dd r set v dcp set dvr_ out av dd i out r 1 r 2 v sat v set = v dcp = i out * r set q1 a1 v out vcom_out in n gnd a2 i dvr_out i dvrout v dcp r set ------------- registervalue 1 + 256 -------------------------------------------------- - ?? ?? av dd 20 -------------- ?? ?? 1 r set ------------ - ?? ?? == (eq. 2)
isl24211 7 fn7585.0 february 23, 2011 the maximum value of i dvr_out can be calculated by substituting the maximum register value of 255 into equation 2, resulting in equation 3: equation 2 can also be used to calculate the unit sink current step size per register code , resulting in equation 4: determination of r set the ultimate goal for the isl24211 is to generate an adjustable voltage between two endpoints, v com_min and v com_max , with a fixed power supply voltage, av dd . this is accomplished by choosing the correct values for r set , r 1 and r 2 . the exact value of r set is not critical. values from 1k to more than 100k will work under most conditions. the following expression calculates the minimum r set value: note that this is the absolute minimum value for r set . larger r set values reduce quiescent power, since r 1 and r 2 are proportional to r set . the isl24211 is tested with a 5k r set . determination of r 1 and r 2 with av dd , v com(min) and v com(max) known and r set chosen per the above requirements, r 1 and r 2 can be determined using equations 6 and 7: final transfer function the voltage at dvr_out can be calculated from equation 8: with amplifier a2 in the unity-gain configuration (v com_out tied to in n as shown in figure 5), v dvrout =v com_out =v com . example as an example, suppose the a vdd supply is 15v, the desired v com_min = 6.5v and the desired v com_max = 8.5v. r set is arbitrarily chosen to be 7.5k . first, verify that our chosen r set meets the minimum requirement described in equation 5: using equations 6 and 7, calculate the values of r 1 and r 2 : table 1 shows the resulting v com voltage as a function of register value for these conditions. output voltage span calculation it is also possible to calculate v com(min) and v com(max) from the existing resistor values. v com_min occurs when the greatest current, i dvr(max), is drawn from the middle node of the r1/r2 divider. substituting registervalue = 255 into equation 8 gives the following: similarly, registervalue = 0 for v com(max) : i dvrout max () a vdd 20r set -------------------- = (eq. 3) i step av dd 256 () 20 () r set () --------------------------------------------- - = (eq. 4) r set min () av dd 16 -------------- v out min () av dd 20 -------------- ? ?? ?? ----------------------------------------------------- - ?? ?? ?? ?? ?? ?? k () = (eq. 5) r 1 5120 r set v com max () v com min () ? 256 v com max () ? v com min () ? -------------------------------------------------------------------------------- - ?? ?? ?? ? = (eq. 6) r 2 5120 r set v com max () v com min () ? 255 av dd ? v com min () 256 v com max () ? ? + -------------------------------------------------------------------------------------------------------------------- - ?? ?? ?? ? = (eq. 7) v dvrout av dd r 2 r 1 r 2 + -------------------- ?? ?? ?? 1 registervalue 1 + 256 -------------------------------------------------- - r 1 20r set -------------------- ?? ?? ?? ? ?? ?? ?? = (eq. 8) table 1. example v dvr_out vs register value register value v dvr_out (v) 08.49 20 8.34 40 8.18 60 8.02 80 7.87 100 7.71 120 7.55 127 7.50 140 7.40 160 7.24 180 7.09 200 6.93 220 6.77 240 6.62 255 6.50 7.5k () r set min () 15 16 ------ - 6.5v 15 20 ------ - ? ?? ?? ------------------------------ ?? ?? ?? ?? ?? 0.163k == ?? ?? ?? ?? ?? > (eq. 9) r 1 5120 7500 8.5 6.5 ? 256 8.5 ? 6.5 ? ------------------------------------- - ?? ?? ?? 35.4k == (eq. 10) r 2 5120 7500 8.5 6.5 ? 255 15 ? 6.5 256 8.5 ? ? + ------------------------------------------------------------------ ?? ?? ?? 46.4k == (eq. 11) v com min () av dd r 2 r 1 r 2 + -------------------- ?? ?? ?? 1 r 1 20r set -------------------- ?? ?? ?? ? ?? ?? ?? = (eq. 12) v com max () av dd r 2 r 1 r 2 + -------------------- ?? ?? ?? 1 1 256 ---------- r 1 20r set -------------------- ?? ?? ?? ? ?? ?? ?? = (eq. 13)
isl24211 8 fn7585.0 february 23, 2011 by finding the difference of equation 13 and equation 12, the total span of v com can be found: assuming that the i dvrout (min) = 0 instead of i step , the expression in equation 14 simplifies to: dvr_out pin leakage current when the voltage on the dvr_out pin is greater than 10v, an additional leakage current flows in to the pin in addition to the i set current. figure 6 shows the i set current and the dvr_out pin current for dvr_out pin voltage up to 19v. in applications where the voltage on the dvr_out pin will be greater than 10v, the actual output voltage will be lower than the voltage calculated by equation 8. the graph in figure 6 was measured with r set = 4.99k . power supply sequence the recommended power supply sequencing is shown in figure 7. when applying power, v dd should be applied before or at the same time as av dd . the minimum time for t vs is 0s. when removing power, the sequence of v dd and av dd is not important. do not remove v dd or av dd within 100ms of the start of the eeprom programming cycle. removing power before the eeprom programming cycle is completed may result in corrupted data in the eeprom. operating and programming supply voltage and current to program the eeprom, av dd must be 10.8v. if programming is not required, the isl24211 will operate over an av dd range of 4.5v to 19v. during eeprom programming, i dd and i avdd will temporarily be higher than their quiescent curre nts. figure 8 shows a typical i dd and i avdd current profile during eeprom programming. the current pulses are erase and write cycles. the eeprom programming algorithm is shown in figure 9. the algorithm attempts up to 4 erase cycles and 4 programming cycles, however typical parts only require 1 cycle of each, sometimes 2 when av dd is near the minimum 10.8v limit. v com span av dd r 2 r 1 r 2 + -------------------- ?? ?? ?? 1 1 256 ---------- ? ?? ?? r 1 20r set -------------------- ?? ?? ?? = (eq. 14) v com span r 1 r ? 2 r 1 r 2 + -------------------- ?? ?? ?? av dd 20r set -------------------- ?? ?? ?? r 1 r ? 2 r 1 r 2 + -------------------- ?? ?? ?? i dvrout max () == (eq. 15) figure 6. dvr_out pin leakage current 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0 2 4 6 8 10 12 14 16 18 20 out pin voltage (v) current (ma) out pin current set pin current register = 255 v dd a vdd t vs figure 7. power supply sequence vdd programming current ~1ms avdd programming current i p 100ms max 2.7ma 200a 50a 90a 25a figure 8. i dd and i avdd current profile during eeprom programming
isl24211 9 fn7585.0 february 23, 2011 isl24211 programming the isl24211 accepts i 2 c bus address and data when the wp pin is high. the isl24211 ignores the i 2 c bus when the wp pin is low. figure 10 shows the serial data format for writing the register and programming the eeprom. figure 11 shows the serial data format for reading the dac register. table 2 shows the truth table for reading and writing the device. programming the eeprom memory transfers the current dac register value to the eeprom and occurs when the control bits select the programming mode and the av dd voltage is >10.8v. after the eeprom programming cycle is started, the wp pin can be returned to logic low while the eeprom write completes, which takes a maximum of 100ms. the isl24211 uses a 6-bit i 2 c address, which is ?100111yx? for the first transmitted byte. bit x is the r/w bit, and bit y is the lsb (d0) of the dcp register code to be written. the complete read and write protocol is shown in figures 10 and 11. i 2 c bus signals the isl24211 uses fixed voltages for its i 2 c thresholds, rather than the percentage of v dd described in the i 2 c specification (see table 3). this should not ca use a problem in most systems, but the i 2 c logic levels in a specific design should be checked to ensure they are compatible with the isl24211. figure 9. eeprom programming flowchart erase pulse start eeprom programming are eeprom cells erased? no yes write pulse are eeprom cells programmed? eeprom programming complete no yes table 2. isl24211 read and write control wp pin r/w p function 0 1 x read register. 0 0 1 will acknowledge i 2 c transactions. will not write to register. 0 0 0 will acknowledge i 2 c transactions. will not write to eeprom. 1 1 x read dac register. 101write dac register. 100program eeprom. table 3. isl24211 i 2 c bus logic levels symbol isl24211 i 2 c standard v il_i2c 0.55v 0.3*v dd v ih_i2c 1.44v 0.7*v dd
isl24211 10 fn7585.0 february 23, 2011 i 2 c read and write format figure 10. i 2 c write format 6 bit address start r/w ack data p ack data lsb stop 10 011 1 0 d0 d7 d6 d5 d4 d3 d2 d1 p isl24211 i 2 c write r/w = 0 = write r/w = 1 = read byte 1 byte 2 msb lsb msb lsb when r/w = 0 p = 0: program eeprom p = 1: write register start ack ack stop figure 11. i 2 c read format 6 bit address start r/w ack data ack x stop 10 011 1 1 xd7d6d5 d4 d3 d2 d1 isl24211 i 2 c read d0 start byte 1 byte 2 msb lsb msb lsb r/w = 0 = write r/w = 1 = read ack start ack stop start
isl24211 11 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7585.0 february 23, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl24211 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/sear revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change 2/23/11 fn7585.0 initial release.
isl24211 12 fn7585.0 february 23, 2011 package outline drawing l10.3x3a 10 lead thin dual flat no-lead plastic package rev 5, 3/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view index area (10 x 0.50) (2.90) ( 8x 0 .50 ) ( 10x 0.25 ) (1.50) 0 . 05 max. 0 . 00 min. 0 . 2 ref 5 (4x) ( 2.30 ) 3.00 0.15 0 .80 max 2.30 10 see detail "x" 0.10 c 5 1.50 index area b 3.00 a pin 1 6 pin 1 6 1 2.0 ref 8x 0.50 bsc 5 c seating plane c 0.08 b c 0.10 m a 10 x 0.25 4 m 0.05 c 10x 0 . 30 c angular 2.50 compliant to jedec mo-229-weed-3 except exposed pad length (2.30mm). 7.

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